This nonprovisional application incorporates by reference the subject matter of Application No. 2000-34321 filed in Korea on Jun. 21, 2000, on which a priority claim is based under 35 U.S.C. xc2xa7119(a).
1. Field of the Invention
The present invention relates to a met hod for fabricating a MOSFET device, and more particularly to fabrication method for a MOSFET device having a metal gate capable of forming a ultra shallow junction and allowing application of a self-aligned contact process.
2. Description of the Related Art
As well known, gates are mainly made of polysilicon. This is because the polysilicon sufficiently meets desired properties required for gates, for example, high melting point, easy formation of thin films, easy patterning of lines, maintenance of stability in an oxidation atmosphere, and formation of planarized surfaces. Where such polysilicon gates are practically applied to MOSFET devices, they obtain a desired conductance by containing a dopant such as phosphorous (P), arsenic (As), or boron (B).
As the degree of integration of semiconductor devices increases, this results in a reduction in the value of certain parameters, such as the line width of gates, the thickness of gate insulating films, or the junction depth, in those semiconductor devices. For this reason, where highly integrated semiconductor devices are fabricated using polysilicon, it is difficult to realize a low resistance required in association with a micro line width. Thus, it is required to develop gates made of a new material substituted for polysilicon.
At the early stage of this development, active research and development efforts have been made in association with polycide gates made of a transition metal-silicide material. However, such polycide gates have a limitation in realizing a low resistance due to the fact that polysilicon still remains in those gates. To this end, active research and development have recently been directed at metal gates.
Where such a metal gate is made of a metal having a work function value corresponding to the mid band-gap of silicon, it can be fabricated into a single gate usable for both the NMOS type and the PMOS type. The metal having a work function value corresponding to the mid band-gap of silicon may include tungsten (W), tungsten nitride (WN), titanium (Ta), titanium nitride (TiN), molybdenum (Mo), tantalum (Ta), and tantalum nitride (TaN).
Where such a metal gate is practically applied to the manufacture of MOSFET devices, however, it has problems involved in the progression of processes, such as a difficulty in etching an associated metal film, damage to an associated silicon substrate during the etching process, and thermal damage resulting from thermal process conducted following the etching process.
For this reason, it is difficult to form such a metal gate using conventional gate formation processes. To this end, a method has been proposed in which metal gates are formed using a damascene process mainly used in the formation of metal lines.
As well known, since this metal gate formation method using the damascene process involves no etching process, it has advantages of preventing damage generated in a silicon substrate while being capable of using the conventional MOSFET process as it is.
Now, a conventional method for fabricating MOSFET device having a metal gate using a damascene process will be described in conjunction with FIGS. 1A to 1E.
Referring to FIG. 1A, a silicon substrate 1 is prepared which has field oxide films 2 defining an active region. A thermal oxide film 3 is formed on the silicon substrate 1 to cover the active region. Thereafter, a polysilicon film 4 and a hard mask film 5 are sequentially deposited over the field oxide film 2 and the thermal oxide film 3.
Referring to FIG. 1B, a hard mask pattern 5a is formed by patterning the hard mask film in accordance with a well-known photolithography process. The polysilicon film 4 and the thermal oxide film 3 are then etched under the condition in which the hard pattern 5a is used as an etch mask. As a result, a sacrificial gate 4a is formed. Desired impurity ions are implanted in a low concentration into portions of the silicon substrate, respectively arranged at opposite sides of the sacrificial gate 4a. A spacer 6 is formed on side walls of laminated sacrificial gate 4a and side walls of the hard mask pattern 5a and then, desired impurity ions are implanted in a high concentration, thereby forming source/drain regions 7 having a Lightly Doped Drain (LDD) structure.
Referring to FIG. 1C, an interlayer insulating film 10 is deposited over the resultant substrate, thereafter, the interlayer insulating film 10 and the hard mask pattern 5a are polished in accordance with a CMP process using the sacrificial gate 4a as a polishing stop layer. As a result, the interlayer insulating film 10 is planarized and the sacrificial gate 4a is exposed.
Referring to FIG. 1D, the exposed sacrificial gate and the thermal oxide film are removed, as a result, a groove C defining a region where a metal gate is to be formed is obtained. A gate insulating film 11 is subsequently formed on the resultant structure to have a uniform thickness, and then a metal film 12 for gate is deposited to completely fill the groove.
Referring to FIG. 1E, a metal gate 12a is formed by polishing the tungsten film 12 and the gate insulating film 11 using the interlayer insulating film 10 as a polishing stop layer, as a result, MOSFET device having a metal gate 12a is obtained.
The conventional method for fabricating MOSFET device has no significant problems. However, the junction produced is not an ultra shallow junction as is required in a highly integrated device. For this reason, additional processes are required to form elevated source/drain regions.
Moreover, the conventional method has a disadvantage that it can not be applied to a self aligned contact (SAC) process as a following process. That is, for example, where a mis-alignment of light exposure mask is generated during SAC process, as shown in FIG. 2, an electrical short is generated between the metal gate 12a and the contact plug 15. Thus, this MOSFET device involves a degradation in reliability and characteristics. In FIG. 2, a reference numeral 14 denotes an insulating film.
As shown in FIG. 3, an electrical short between the metal gate 12a and the contact plug 15 due to the mis-alignment of the light exposure mask can be avoided by forming a SAC barrier film 13 made of nitride film. However, for the formation of such an SAC barrier film, it is necessary to use a subsequent process involving a plurality of processing steps, for example, etching a metal gate, depositing a nitride film and polishing the nitride film, thereby resulting in an increase in the manufacturing time and costs of the MOSFET device. In particular, it is difficult to form an SAC barrier film made of nitride film due to the difficulties involved in etching all metal gates to have a uniform etch depth and in polishing a nitride film.
As a result, a MOSFET device having a conventional metal gate has disadvantages that additional processes are required to form an ultra shallow junction and that a subsequent SAC process cannot be applied unless an SAC barrier film is also formed on the metal gate.
Therefore, an object of the invention is to provide a method for fabricating a MOSFET device having a metal gate, capable of forming an ultra shallow junction and allowing subsequent application of an SAC process.
In accordance the present invention, this object is accomplished by providing a method for fabricating a MOSFET device (and the MOSFET device itself) comprising: forming a sacrificial gate on an active region of a silicon substrate; forming a first silicon epitaxial layer, thinner than the sacrificial gate, on the silicon substrate at opposite sides of the sacrificial gate to cover the active region; forming elevated source/drain regions on the silicon substrate, respectively arranged at opposite sides of the sacrificial gate by implanting desired impurity ions into the silicon substrate via the first silicon epitaxial layer; forming an interlayer insulating film on the resultant structure; polishing the interlayer insulating film to expose the sacrificial gate; removing the exposed sacrificial gate to form a groove defining a region where a metal gate is to be formed; forming a gate insulating film and a metal film on the resultant structure sequentially; forming a metal gate within the groove by polishing the metal film, the gate insulating film and the interlayer insulating film until the first silicon epitaxial layer is exposed; and forming a second silicon epitaxial layer on the first silicon epitaxial layer.
Advantages of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.